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Initial responsibilities for the Technical Services Engineer will be to perform Logistics Support Analysis (LSA) activities. Position will lead into responsibilities ...
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**This position requires an ACTIVE SECRET level security clearance to even be considered. If you do NOT possess at least that first requirement, PLEASE DO NOT ...
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For your reference, we have included the original job posting below.
Engineer - ASIC Design Sr.
Job Number:
22806344
Company Name:
SafeNet Inc.
Job Location:
Torrance, CA US
Job Category:
Information Technology
Engineer - ASIC Design Sr.
Engineer - ASIC Design Sr.
Job ID: 1330 # Positions: 1 Location: US-CA-Torrance Experience (Years): 5 Posted Date: 2/24/2010 Category: ENGINEERING - Electrical Engineering Position Type: Full Time Hire Type: New Security Clearance: Active Secret Travel: less than 25% Job Type: Direct
Apply for this job: Your application choices are: * Apply for this jobonline * Send your resume as an attachment viae-mail * Refer a friend to this job More information about this job: Overview: SafeNet Employment GET INSIDE At SafeNet, our goal is to employ the brightest and most talented people in the industry. With more than 30 offices worldwide and more than 1,100 employees, we know the importance of hiring the very best to make our company succeed. No matter what the job is-Tech Writer, Software Engineer, or Customer Service Rep-we're always looking for our future leaders. If you're seeking a challenging career and would like the opportunity to advance, then SafeNet may be right for you. SafeNet, get inside. ASIC Design Engineer Summary: Perform tasks of significant scope within the definition/planning, implementation/verification and test portions of the ISO 9001 ASIC development flow under general supervision requiring a high degree of technical competence. These tasks may require requirements analysis, resource/tool/equipment identification, schedule development, architecture definition, ASIC specification, HDL (Hardware Description Language) design entry, functional simulation, netlist synthesis, RTL and gate-level simulation, system-level simulation, static timing analysis, test vector generation, prototype characterization and system board test. Qualification Requirements: Education: Bachelor of Science in Electrical Engineering, Computer Science, other related discipline or equivalent experience. Preferred Master of Science or PhD Experience: BS- 4-6 years of applicable ASIC development experience. MS- 2-4 years of applicable ASIC development experience. PhD- 0-2 years of applicable ASIC development experience. Skills: Knowledge of theory and practice in some areas within the professional field. Team work and good communication skills Ability to apply theory and practice under close supervision for project success and a quick learner. Good design debugs skills. Familiar with Modelsim, Synopsys DC compiler and Synopsys Primetime tools.
Responsibilities: Essential Duties & Responsibilities include, but are not limited to the following: Requires skill in all phases of ASIC design; detailed design requirements, architecture design, VHDL or Verilog RTL detailed design, simulation, synthesis, timing analysis, test vector generation; creating simulation and prototype verification test plans, conduction hardware design demo, participating in design reviews; experienced in requirements definition and architecture to net-list approval and ASIC buy-off; experience with Cryptography; FPGA place and route, timing analysis and test; debug skills. Working knowledge of VHDL language, ARM7, ARM9, RISC processor, USB, network architecture, space radiation harden design, FPGA design tools and flow.
Qualifications: Employees must be US citizens, without dual citizenship in another country. Competitive salary and benefits package offered including bonus program, and 401(k) match. SafeNet is an Equal Opportunity Employer
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