Analog Mixed-Signal Modeling Verification Engineer
Santa Clara Valley (Cupertino),California,United States
We want you to have 5+ years of industry verification experience with RF/Mixed-Signal blocks and SOCs.
Expertise building Mixed-Signal test benches, checkers and tests.
Solid experience with creating and using real-numbered analog behavioral models in SystemVerilog or other language.
Experience in HVL and HDL (SystemVerilog, Verilog).
Strong verification skills in problem solving, constrained random testing, and debugging.
Good understanding of common analog/RF blocks.
Experience with HVL methodology (UVM/OVM/VMM) a plus.
Experience with signal processing using Python or Matlab a plus.
Experience with Virtuoso Composer, ADE and HED a plus.
Team spirit, excellent communication skills and the desire to take on diverse challenges are essential to have.
Education & Experience
MSEE is required; PhD would be an advantage.
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